VHDL-FPGA-Verilog List Page 4043

VHDL-FPGA-Verilog list

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Sin_wave Downloaded：0: sin waveform signal from the procedure described in VHDL language Quartus
Update : 2025-01-13 Size : 472kb Publisher : luyingc
UART_VHDL Downloaded：0: URAT asynchronous communication interface VHDL description can be integrated
Update : 2025-01-13 Size : 652kb Publisher : luyingc
mc8051_design Downloaded：0: This is version 1.4 of the MC8051 IP core.
Update : 2025-01-13 Size : 764kb Publisher : 俞宏锦
FPGA-Ethernet-video Downloaded：0: Introduce how to realize the network video transmission FPGA design papers, a good reference.
Update : 2025-01-13 Size : 186kb Publisher : 曾祥进
time Downloaded：0: 露脿鹿 | 脛脺脢媒脳脰脢卤脰脫脡猫录脝渭脛脭
Update : 2025-01-13 Size : 218kb Publisher : HY
newboardconfig Downloaded：0: cyclone II 208c8 prepared display image acquisition procedures.
Update : 2025-01-13 Size : 1.72mb Publisher :
The_Verilog_Hardware_Description_Language Downloaded：0: Beginners to learn Verilog language Enlightenment Reader, easy to read
Update : 2025-01-13 Size : 229kb Publisher : 谷牧
spartan3 Downloaded：0: Based on Xilinx
Update : 2025-01-13 Size : 4kb Publisher : 陈想
fsm_cal Downloaded：0: State machine with the realization of a logic operation unit, the logic operation unit has a conventional computing. State machine to ensure that the level of clarity, with gate-level circuit structure which can be direc
Update : 2025-01-13 Size : 14kb Publisher : 陈想
uart Downloaded：0: VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Update : 2025-01-13 Size : 5kb Publisher : 陈想
FFT_report Downloaded：0: Design Simulation and synthesis of a fft processor using VHDL
Update : 2025-01-13 Size : 354kb Publisher : lys
chronograph Downloaded：0: VHDL seconds recorded in a small program (the test, en to enable effective high-end)
Update : 2025-01-13 Size : 7kb Publisher : qlz

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