VHDL-FPGA-Verilog List Page 4146

VHDL-FPGA-Verilog list

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i2c_slave_con Downloaded：0: can support continuous reading i2cslave source, very suitable as a master to the use of testbench
Update : 2025-01-11 Size : 2kb Publisher : uongue
verilogzzhwfy Downloaded：1: QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
Update : 2025-01-11 Size : 5kb Publisher : 周正华
VERILOGCOMP Downloaded：0: design a byte (8) for comparison. Requirements : To compare the size of two bytes, as a greater than [7:0] b [7:0] output margin. Otherwise, low-level output, rewritten test model, in order to enable them to conduct more
Update : 2025-01-11 Size : 7kb Publisher : 周正华
VERILOGTIME Downloaded：0: use 10M clock, the design of a single-cycle waveform cycle
Update : 2025-01-11 Size : 5kb Publisher : 周正华
VERILOGBLOCK Downloaded：0: in blocking module by the following wording, simulation and synthesis of the results will be what kind of changes? Make simulation waveform analysis and comprehensive results.
Update : 2025-01-11 Size : 9kb Publisher : 周正华
VERILOGSELE Downloaded：0: always use a block design options for the Eighth Route Army data. Requirements : every road input data and output data are four two-band number, When choosing to switch (at least three), or changes in the input data, out
Update : 2025-01-11 Size : 14kb Publisher : 周正华
modelsim_userguide Downloaded：0: MODELSIM simulation software users manuals, MODELSIM users to be of much help.
Update : 2025-01-11 Size : 3.72mb Publisher : liujie
sdr_sdram Downloaded：0: detailed SDRAM controller HDL code top-level code, it was very clear
Update : 2025-01-11 Size : 3kb Publisher : 陈建勇
sdr_data_path Downloaded：0: SDRAM controller Verilog code, data link module, complete and top-level module data exchange -SDRAM controller member Verilog code, data link module, Top module completed and the data exchange
Update : 2025-01-11 Size : 2kb Publisher : 陈建勇
control_interface Downloaded：0: SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
Update : 2025-01-11 Size : 3kb Publisher : 陈建勇
Commandinterface Downloaded：0: SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
Update : 2025-01-11 Size : 7kb Publisher : 陈建勇
verilogclock Downloaded：0: if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.
Update : 2025-01-11 Size : 3kb Publisher :

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