VHDL-FPGA-Verilog List Page 4175

VHDL-FPGA-Verilog list

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UART_ise7_bak Downloaded：0: using FPGA full-duplex asynchronous serial port (UART), and PC communication. An initiation; 8 data spaces; One-stop; No Parity; Baud Rate for 2400,4800,9600, 11520 optional or variable (baud rate can be used to control
Update : 2025-01-10 Size : 32kb Publisher : lee
mouse_control Downloaded：0: one with FPGA PS/2 mouse interface. 2, the left mouse button pressed cruciform images in the middle mouse to change the color box, press the right arrow at the change in color. 3, Reset buttons : the total reduction.
Update : 2025-01-10 Size : 9kb Publisher : lee
mcnc Downloaded：0: eyebrows from overseas sites from the next, oh, I hope Members can support ...!
Update : 2025-01-10 Size : 55kb Publisher : 谢敏
CPLDxiaoche Downloaded：0: intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent,
Update : 2025-01-10 Size : 1kb Publisher : lili
adder_4bit Downloaded：0: four adder with OrCAD completed, can be used for eight or even 16 Adder design prototype
Update : 2025-01-10 Size : 1kb Publisher : z9z9
SCAN4 Downloaded：0: four signal detector, complete with OrCAD for the input signal and the signal for more monitoring
Update : 2025-01-10 Size : 1kb Publisher : z9z9
conter1 Downloaded：0: a VHDL counter. Can be further converted into actual use of the Counter
Update : 2025-01-10 Size : 1kb Publisher : z9z9
COUNT100 Downloaded：0: a digital counter, every 100 seconds is a pulse output signal can be used for timing control
Update : 2025-01-10 Size : 1kb Publisher : z9z9
SHIFTLNE Downloaded：0: VHDL under the Digital shifter and can be used for rapid multiplication using two 229 hope you like
Update : 2025-01-10 Size : 1kb Publisher : z9z9
I60BCD Downloaded：0: I60BCD is a digital clock display module, you can also modified it into other equipment Display
Update : 2025-01-10 Size : 1kb Publisher : z9z9
AEScoremodules Downloaded：0: AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Update : 2025-01-10 Size : 10kb Publisher : 许茹芸
rs_decoder_31_19_6.tar Downloaded：1: Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) =
Update : 2025-01-10 Size : 14kb Publisher : 许茹芸

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