VHDL-FPGA-Verilog List Page 4170

VHDL-FPGA-Verilog list

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N_counter_VHDL Downloaded：0: arbitrary N divider 229 standard VHDL code (original)
Update : 2025-01-10 Size : 1kb Publisher : 汤维
PulseWidth_detector_VHDL Downloaded：0: communication control used in pulse width detection procedures, VHDL modular organization to achieve (original)
Update : 2025-01-10 Size : 1kb Publisher : 汤维
even_divider_VHDL Downloaded：0: used 2,4,6 and even arbitrary divider VHDL code to achieve (original)
Update : 2025-01-10 Size : 1kb Publisher : 汤维
odd_divider_VHDL Downloaded：0: used 1,3,5 and arbitrary odd Divider VHDL code to achieve (original)
Update : 2025-01-10 Size : 1kb Publisher : 汤维
Synthesisofverilog Downloaded：0: a useful comprehensive Verilog language study
Update : 2025-01-10 Size : 266kb Publisher : wrrkaixin
2006829121816 Downloaded：0: simple logic analyzer with the design of the source code for electronic 05 2 Prize Competition works
Update : 2025-01-10 Size : 198kb Publisher : 邓勇
9.1_ONE_PULSE Downloaded：0: based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by the temporal flow chart 9.1.2 9.1.3 System Design Description logic diagram 9.1.5 9.1.4 Delay Module de
Update : 2025-01-10 Size : 4kb Publisher : 宁宁
9.2_LCD_PULSE Downloaded：0: based on Verilog-HDL hardware Circuit of 9.2 LCD display module with the series Single-Pulse Generator 9.2.1 LCD display module Principle 9.2.2 shows the logic design Thinking and Process 9.2.3 LCD display module hardwar
Update : 2025-01-10 Size : 5kb Publisher : 宁宁
9.3_Pulse_Counter Downloaded：0: based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5-
Update : 2025-01-10 Size : 4kb Publisher : 宁宁
9.4_PULSE_FRE Downloaded：0: based on Verilog-HDL hardware Circuit of 9.4 pulse frequency measurement and display 9.4.1 pulse frequency measurement frequency 9.4.2 principle, the principle 9.4.3 Frequency Measurement Module Design and Implementation
Update : 2025-01-10 Size : 2kb Publisher : 宁宁
9.5_PULSE_WIDTH Downloaded：0: based on Verilog-HDL hardware Circuit of 9.5 pulse cycle of measurement and display 9.5.1 pulse cycle 9.5.2 cycle measurement principle, the principle 9.5.3 cycle measurement Module Design and Implementation 9.5.4 statem
Update : 2025-01-10 Size : 5kb Publisher : 宁宁
9.6_PULSE_Level Downloaded：0: Verilog-HDL-based hardware circuits to achieve 9.6 high and low pulse duration measurement and 9.6.1 show the high and low pulse duration of the working principle of measuring the high-low 9.6.2 duration measurement modu
Update : 2025-01-10 Size : 5kb Publisher : 宁宁

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