VHDL-FPGA-Verilog List Page 4165

VHDL-FPGA-Verilog list

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clockdesign Downloaded：0: based on SMART- I platform clock circuit design and implementation vhdl use simulation program, and download realization function correctly
Update : 2025-01-10 Size : 301kb Publisher : 刘素珍
ModelSim_foundation Downloaded：0: with practical examples of simulation software modelsim use of the basic method applied to beginners
Update : 2025-01-10 Size : 94kb Publisher : 刘素珍
NAND01GR3B_VH1 Downloaded：0: nand flash NAND01GR3B (st), the simulation model (VHDL)
Update : 2025-01-10 Size : 129kb Publisher : chen
ddr_cntl_a_withtb Downloaded：0: arm control FPGA DDR test code sharing what
Update : 2025-01-10 Size : 2.27mb Publisher : yourname
4bitadd Downloaded：0: four full adder original code, including the simulation code and four counter code.
Update : 2025-01-10 Size : 3kb Publisher :
xuhuanjiucuo Downloaded：0: cycle error correction decoder VHDL code. Communications FPGA design code base.
Update : 2025-01-10 Size : 3kb Publisher :
traffic_control Downloaded：0: design a crossroads for the traffic signal controller is a group in green, yellow and red lights to direct traffic. green, yellow and red, respectively for the duration of 20 seconds, five seconds and 25 seconds; When sp
Update : 2025-01-10 Size : 2kb Publisher : 飘来的南风
serial_produce Downloaded：0: to design an 24-1 since the start of the pseudo-random number (111101011001000) generator. Design of a signal sequence generator to produce a sequence code 011100110011. Implementation sequence 1110100. Test sequence cod
Update : 2025-01-10 Size : 52kb Publisher : 飘来的南风
multiple_pathanddopple Downloaded：0: Based on Multi-Drive transmission and Doppler frequency shift of the Rayleigh (Rayleigh) channel simulation main consideration different The simulation conditions
Update : 2025-01-10 Size : 116kb Publisher : 飘来的南风
verilog_hdl_example Downloaded：0: verilog_hdl Guide 135 cases, the source, there is a need to look at the download
Update : 2025-01-10 Size : 154kb Publisher : 磊
D_Clock Downloaded：0: digital clock is the main function Minutes date when the output function and the date and time set for the function , they can point the entire timekeeping functions. Digital Clock Design is the core issue date of the cl
Update : 2025-01-10 Size : 372kb Publisher : 送水的
D_f_apparatus Downloaded：0: frequency measurement and measurement cycle is the basic method used to a fixed clock as a reference clock, measured single cycle to cycle counting, the counting unit time for the frequency. However, due to the frequency
Update : 2025-01-10 Size : 100kb Publisher : 送水的

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