VHDL-FPGA-Verilog List Page 421

VHDL-FPGA-Verilog list

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basys3_timing Downloaded：0: Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL
Update : 2025-01-19 Size : 692kb Publisher : 王柄杰
vga2 Downloaded：0: This function is mainly to achieve a VGA display with a resolution of 1024* 768, the bag has produced a good coe file into the rom, for xilinx chip
Update : 2025-01-19 Size : 689kb Publisher : liyi
zhuangtai Downloaded：0: This program implements packets, in the communication transmission is often used, the use of chip xilinx, verilog language
Update : 2025-01-19 Size : 49kb Publisher : liyi
shuma Downloaded：0: This program uses xilinx chip, verilog written realize digital functions, digital control for the common anode digital tube, you can transform the UFC pin definitions to adapt their own development boards
Update : 2025-01-19 Size : 314kb Publisher : liyi
fifo Downloaded：0: The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language
Update : 2025-01-19 Size : 3.6mb Publisher : liyi
liushui Downloaded：0: This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language
Update : 2025-01-19 Size : 71kb Publisher : liyi
float_add_module Downloaded：0: 32bits float add module use Verilog HDL.
Update : 2025-01-19 Size : 2kb Publisher : 刘磊
fenpin Downloaded：0: Output than the set of 8 times the clock frequency of the clock, to achieve frequency division function, can be used for chip control.
Update : 2025-01-19 Size : 9kb Publisher : 高
ad-kongzhi Downloaded：0: Mainly used for the control of AD, including the clock settings and the output address of the control.
Update : 2025-01-19 Size : 10kb Publisher : 高
bixiang Downloaded：0: The main function of the program is to achieve the phase comparison of the two waveforms, and the transmission of the square wave.
Update : 2025-01-19 Size : 10kb Publisher : 高
hecheng Downloaded：0: The program and algorithm two wave signal synthesis is a square wave output.
Update : 2025-01-19 Size : 9kb Publisher : 高
FIFO Downloaded：0: FPGA FIFO
Update : 2025-01-19 Size : 2.72mb Publisher : liuky

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