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VHDL-FPGA-Verilog list
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design for ADC base on matlab and simulink。it is very good for you when you start your project。
Update : 2025-01-19 Size : 175kb Publisher : 君子剑

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SONY CCD DIRIVER,VERILOG
Update : 2025-01-19 Size : 98kb Publisher : 444444

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Infrared detector drive to achieve front-end image acquisition, to achieve front-end collection of infrared thermal imaging lens.
Update : 2025-01-19 Size : 3kb Publisher : 张德洲

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Use Verilog implementation of asynchronous fifo functionality
Update : 2025-01-19 Size : 1.15mb Publisher : Amy_nmw

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Synchronous FIFO has been fully validated
Update : 2025-01-19 Size : 132kb Publisher : seer

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ep1c3 realize ps2,ep 1c3 realize ps2
Update : 2025-01-19 Size : 221kb Publisher : davidobt

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EP1C3-uart 1 verilog, implements a program to send and receive a 10 bit (that is, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Baud-law decided by div_par parameters defined in the pr
Update : 2025-01-19 Size : 334kb Publisher : davidobt

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ep1c3-seg1 vhdl, 7-segment LED Experiment 2: incrementally on four digital display counts up 0000-0001-> 0002 ...... ..9999 ... ... .0001 ... of 0000h. - Design of a 4-digit decimal counter, and with a digital display of
Update : 2025-01-19 Size : 167kb Publisher : davidobt

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VGA IP used to connect the FPGA and VGA
Update : 2025-01-19 Size : 1kb Publisher : Rachid_Allaoui

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altera PCIe Ttransfer code。
Update : 2025-01-19 Size : 8.95mb Publisher : shen xiaoyu

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UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, ////////////////
Update : 2025-01-19 Size : 52kb Publisher : qiubin

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Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301
Update : 2025-01-19 Size : 2kb Publisher : songjunkai
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