VHDL-FPGA-Verilog List Page 4224

VHDL-FPGA-Verilog list

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8051VHDL Downloaded：0: C8051 core of a VHDL source code
Update : 2024-12-28 Size : 411kb Publisher : ydx
ccpu Downloaded：0: this is a done VERILOG eight functional weak CPU
Update : 2024-12-28 Size : 16kb Publisher : 贾振华
pluse_delay Downloaded：0: using VHDL-trigger circuit stability, steady time for the whole system clock several times.
Update : 2024-12-28 Size : 87kb Publisher : david
vhdlprogram Downloaded：0: with complex programmable logic devices (CPLD) with a digital clock control system
Update : 2024-12-28 Size : 5kb Publisher : 王永
FIR_1 Downloaded：0: FIR filter Verilog, has implemented six lines of program design.
Update : 2024-12-28 Size : 1kb Publisher : 李甫
TI6713DSKVHDL Downloaded：0: TI6713 floating-point DSP DSK VHDL. More comprehensive. Compiler can run.
Update : 2024-12-28 Size : 31kb Publisher : 丁德锋
n_dc_motor Downloaded：0: VHDL achieved DC Motor Controller General of different procedures they simply/cpld. may need to amend some source code.
Update : 2024-12-28 Size : 2kb Publisher : 刘挺
source_verilog Downloaded：0: Verilog realized Adder (8) applies to beginners blends
Update : 2024-12-28 Size : 156kb Publisher : 高浪
sdramcore Downloaded：0: SDRAM control of the kernel, the top series, has been tuned, no errors
Update : 2024-12-28 Size : 19kb Publisher : 韩
air_controller Downloaded：0: this as an air-conditioning controller, is to use the FPGA to realize that he can complete the indoor temperature adjustment.
Update : 2024-12-28 Size : 107kb Publisher : kyhh
MAX_II_board_schematics Downloaded：0: Altera's MAX II development board schematics
Update : 2024-12-28 Size : 236kb Publisher : 周宇
CPLD_CCD Downloaded：0: based CPLD CCD Acquisition System Design FOSS
Update : 2024-12-28 Size : 65kb Publisher : 周宇

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