VHDL-FPGA-Verilog List Page 4231

VHDL-FPGA-Verilog list

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frame_sync Downloaded：1: frame synchronization module Veriolog source. The ModelSim of a project. A test document.
Update : 2024-12-26 Size : 24kb Publisher : 刘仪
hamin0132 Downloaded：0: series guitar code modules, using Verilog languages, as Modelsim of a project.
Update : 2024-12-26 Size : 31kb Publisher : 刘仪
QPSK2154 Downloaded：1: QPSK VERLOG source of the MODELSIM of a project, test vector.
Update : 2024-12-26 Size : 23kb Publisher : 刘仪
dll11254 Downloaded：0: digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
Update : 2024-12-26 Size : 19kb Publisher : 刘仪
crc3321 Downloaded：0: Cyclic Check Code VERILOG source, the MODELSIM of a project.
Update : 2024-12-26 Size : 26kb Publisher : 刘仪
parity2258 Downloaded：0: parity VERILOG source code for MODELSIM of a project. A test document.
Update : 2024-12-26 Size : 25kb Publisher : 刘仪
EDATOOL Downloaded：0: introduced EDA tools (Word stalls) lt; No extract passwords gt;
Update : 2024-12-26 Size : 16kb Publisher : 韓堇
Full_Adder Downloaded：0: full adder and the VHDL_CODE TEST_BENCH not extract passwords
Update : 2024-12-26 Size : 1kb Publisher : 韓堇
time_display&alarm_clock Downloaded：0: this experiment for the board through the alarm clock procedures were used ASM source VHDL and depicts, but the two procedures different functions.
Update : 2024-12-26 Size : 2kb Publisher : 陈谷
program_all Downloaded：0: this document for many years I collected subroutine module source code, the application for beginners. Using a variety of statements depicts a common basic circuit module depicts.
Update : 2024-12-26 Size : 4kb Publisher : 陈谷
I2C_read Downloaded：0: I2C Reading, depicts through the state machine, called Simulation
Update : 2024-12-26 Size : 1kb Publisher : 陈谷
I2C_write Downloaded：0: I2C written procedures, program design using state machine, and through to the output indicator showed the state.
Update : 2024-12-26 Size : 1kb Publisher : 陈谷

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