VHDL-FPGA-Verilog List Page 4237

VHDL-FPGA-Verilog list

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unicntr Downloaded：0: part of the general purpose registers IEEE code LIBRARY USE traffic IEEE.STD_LOGIC_1164.ALL ENTITY IS PORT (clk, sm, sb : IN mr bit, my, mg, br, by, bg : OUT bit) END traffic
Update : 2024-12-26 Size : 134kb Publisher : 土木文田
hiervhdl Downloaded：0: Using VHDL Design VHDL language beginners paradise
Update : 2024-12-26 Size : 43kb Publisher : 土木文田
T65_v301 Downloaded：0: source like nuclear microprocessor 6050 MCU
Update : 2024-12-26 Size : 28kb Publisher : dong
ACCUME Downloaded：0: stressed Verilog code-writing norms, is often not a popular topic, but it is very necessary. Each has its own code writers in the preparation habits, but like their own habits to prepare
Update : 2024-12-26 Size : 2kb Publisher : 张鹏
verilogexperance Downloaded：0: Verilog hardware description language for the development of some practical experience
Update : 2024-12-26 Size : 5kb Publisher : 王磊
clk_divide_3 Downloaded：0: VHDL prepared three frequency can be extended to achieve arbitrary odd
Update : 2024-12-26 Size : 122kb Publisher : 利津候
quartusii Downloaded：0: recommended !!!!! school ASIC fairly good tutorial! ! ! ! Or can see!
Update : 2024-12-26 Size : 825kb Publisher : 安安
calendar_clock Downloaded：0: using HDL to write electronic calendar, it shows the year, month, day and time, with alarm function
Update : 2024-12-26 Size : 1.7mb Publisher : zz
cardPhone Downloaded：0: card billing telephone circuits, verilogHDL prepared with the major simulate the real phone function
Update : 2024-12-26 Size : 1.65mb Publisher : zz
88_arms_counter Downloaded：0: VHDL source code can be edited in Quartus test, simulation.
Update : 2024-12-26 Size : 5kb Publisher : tom
68_alarm_controller Downloaded：0: VHDL source, the Quartus environment testing, simulation. Has been tested.
Update : 2024-12-26 Size : 3kb Publisher : tom
78_alu_input Downloaded：0: VHDL source, the Quartus environment testing, simulation. Has been tested.
Update : 2024-12-26 Size : 2kb Publisher : tom

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