VHDL-FPGA-Verilog List Page 4240

VHDL-FPGA-Verilog list

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红绿灯控制 Downloaded：0: traffic light control, the changes on the order of traffic lights, changes of time
Update : 2024-12-26 Size : 59kb Publisher : 李继伟
加法 Downloaded：0: test vector Waveform Generator : VHDL example-- Adder source
Update : 2024-12-26 Size : 2kb Publisher : 张洪
blaster-wh Downloaded：0: own download Altera's line, long ago, protel98 Cricket.- Wh
Update : 2024-12-26 Size : 11kb Publisher : 王晗
pinlvji Downloaded：0: the frequency meter is measuring weeks, frequency measurement, measuring the ratio of the basic functions can automatically shift error of 1%
Update : 2024-12-26 Size : 639kb Publisher : 马忠志
[eda]vhdl Downloaded：0: Fuzhou University EDA optional courses in all experimental code. VHDL description (vhd), and circuit (GdF)
Update : 2024-12-26 Size : 217kb Publisher : 林锋杰
Evita_Verilog Downloaded：0: Verilog very handy and easy to teaching software.
Update : 2024-12-26 Size : 3.6mb Publisher : 王虎林
Evita_VHDL Downloaded：0: VHDL very handy and easy to teaching software. We try.
Update : 2024-12-26 Size : 2.86mb Publisher : 王虎林
CPLD_DMA Downloaded：0: This is a ISP1582 USB device DMA transmission of the auxiliary circuit hardware design source code
Update : 2024-12-26 Size : 5kb Publisher : 张国梁
RAMINCREASE Downloaded：0: CPLD This is done using the DSP memory expansion of the source document.
Update : 2024-12-26 Size : 6kb Publisher : 张国梁
primetime Downloaded：0: This is the VHDL language delay the test procedure used to determine the performance CPLD
Update : 2024-12-26 Size : 51kb Publisher : 张国梁
mt48lc2m32b2 Downloaded：0: SDRAM control nuclear, has been tested, we can use a slightly modified
Update : 2024-12-26 Size : 9kb Publisher : 洪戈
SDRAM_C Downloaded：0: SDRAM control core has been tested and can be modified with a slight modification. It has been tested, we can use a slightly modified
Update : 2024-12-26 Size : 1kb Publisher : 洪戈

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