VHDL-FPGA-Verilog List Page 4244

VHDL-FPGA-Verilog list

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USB 2.0 IP Core Downloaded：0: USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
Update : 2024-12-25 Size : 177kb Publisher : 林风
fifo程序 Downloaded：0: using Verilog language in which they simply realize fifo function!
Update : 2024-12-25 Size : 1kb Publisher : 刘涛
k5 Downloaded：0: experimental procedure for FPGA serial communications and computer research
Update : 2024-12-25 Size : 1.04mb Publisher : 仇海亮
用cpld实现曼彻斯特编码 Downloaded：0: cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication
Update : 2024-12-25 Size : 4kb Publisher : 李鹏
异步FIFO存储器的控制设计 Downloaded：0: asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
Update : 2024-12-25 Size : 6kb Publisher : 李鹏
D触发器的设计 Downloaded：0: D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.
Update : 2024-12-25 Size : 3kb Publisher : 李鹏
用一位全加器组成四位全加器 Downloaded：0: All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
Update : 2024-12-25 Size : 3kb Publisher : 李鹏
指令译码电路的设计 Downloaded：0: instruction decoder circuit design. Mainly used in digital circuit design. The language used for Verilog HDL.
Update : 2024-12-25 Size : 4kb Publisher : 李鹏
FIRvhdl Downloaded：0: use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation- 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAXPLUS2 joint design and simulation
Update : 2024-12-25 Size : 3kb Publisher : 达闻西
crc_verilog_xilinx Downloaded：0: CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
Update : 2024-12-25 Size : 10kb Publisher : 李鹏
等精度频率计 Downloaded：1: use of the VHDL language they simply write the application procedures so that such ideas as to accuracy Cymometer
Update : 2024-12-25 Size : 246kb Publisher : 丢丢熊
COUNT_100 Downloaded：0: use Vhdl language FPGA applications, realizing the contents of the 100 NUMBER
Update : 2024-12-25 Size : 181kb Publisher : 丢丢熊

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