VHDL-FPGA-Verilog List Page 427

VHDL-FPGA-Verilog list

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khanom-heydari Downloaded：0: Floaaattiing poiiint for vhd
Update : 2025-01-19 Size : 177kb Publisher : farnaz
polyphaseFIR_1v0 Downloaded：0: polyphase fir dilter
Update : 2025-01-19 Size : 37kb Publisher : arjun
reset_syn Downloaded：0: Reset signal processing, " asynchronous clear, synchronous release" function.
Update : 2025-01-19 Size : 1kb Publisher : 小白
clk_div Downloaded：0: Clock divider function module, after using two different counter or re-shift ways to save resources.
Update : 2025-01-19 Size : 1kb Publisher : 小白
rs422_r Downloaded：0: This function module implements the standard protocols 422 single-byte receive function, using the start bit+ 8 data bits odd parity+1+ stop bits, enabling a serial input parallel output.
Update : 2025-01-19 Size : 2kb Publisher : 小白
rs422_t Downloaded：0: This function module implements the standard protocols 422 single-byte transmit function, the start bit+ 8 data bits odd parity+1+ stop bits, enabling a parallel input serial output.
Update : 2025-01-19 Size : 2kb Publisher : 小白
rx_decode Downloaded：0: Serial reception data decoding function, by state machine, belonging to implement link layer protocol.
Update : 2025-01-19 Size : 2kb Publisher : 小白
cpu Downloaded：0: This a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
Update : 2025-01-19 Size : 7kb Publisher : 耿瑞
traffic_controller Downloaded：0: This a verilog code for a kind of traffic light controller. The code was simulated and verificated on FPGA. When the code works on FPGA, it can be communicated with PC using serial debugging assistant. The PC can set the
Update : 2025-01-19 Size : 7kb Publisher : 耿瑞
uart_fifo Downloaded：0: This a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.
Update : 2025-01-19 Size : 2kb Publisher : 耿瑞
ahb_system_generator_latest.tar Downloaded：0: AHB system generator. This file is a part of a system generator for AHB system. it is VHDL code for the AMBA arbiter.
Update : 2025-01-19 Size : 261kb Publisher : Uthman
msk_modulation Downloaded：0: With verilog hardware description language to write msk modulation process, you can refer
Update : 2025-01-19 Size : 1kb Publisher : yangdong

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