VHDL-FPGA-Verilog List Page 434

VHDL-FPGA-Verilog list

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xilinx_license_2015 Downloaded：0: the license of Vivado Design Suite v2015.4
Update : 2025-01-19 Size : 1kb Publisher : ranbowang
RS_Encode_Decode Downloaded：0: RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.
Update : 2025-01-19 Size : 14kb Publisher : ranbowang
Random_Derandom Downloaded：0: Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.
Update : 2025-01-19 Size : 4kb Publisher : ranbowang
Interleaver_Deinterleaver Downloaded：0: Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.
Update : 2025-01-19 Size : 9kb Publisher : ranbowang
uartlvds Downloaded：0: UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
Update : 2025-01-19 Size : 12kb Publisher : 毕向伟
QPSK Downloaded：0: This the QPSK modulation verilog language written with ISE code
Update : 2025-01-19 Size : 237kb Publisher : 陈磊
conv_encoder(rate=1_2) Downloaded：0: It is written in verilog language ISE convolution coding rate 1/2 code
Update : 2025-01-19 Size : 1.63mb Publisher : 陈磊
AD9854(Altera) Downloaded：0: This is a written in FPGA driver of AD9854, it contains the FSK and PSK, ASK.
Update : 2025-01-19 Size : 391kb Publisher : 隼化劫
anish-bit-masking Downloaded：0: vhdl code for bit masking algorithm
Update : 2025-01-19 Size : 205kb Publisher : gopalakirshnan
05413cordic Downloaded：0: VHDL CODE FOR CORDIC ALGORITHM
Update : 2025-01-19 Size : 140kb Publisher : gopalakirshnan
pll_prj Downloaded：0: Altera FPGA Cyclone
Update : 2025-01-19 Size : 126kb Publisher : 相同
AX301_led_test_code Downloaded：0: AX301 development board LED test code
Update : 2025-01-19 Size : 1kb Publisher : 张天奇

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