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VHDL-FPGA-Verilog list
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Basys 3 oscilloscope source code, can refer to.
Update : 2025-01-21 Size : 1.48mb Publisher : 罗密

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the chip is winbon w25p16. vhdl language. the sysclk is 125m. it is easy to jump to write , read, or erase status by change idle status.
Update : 2025-01-21 Size : 2kb Publisher : 钱愈玉

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Using Quartus ii13.0 write binary adder, using the IP core RAM, and LCD display, open can be used directly.
Update : 2025-01-21 Size : 5.77mb Publisher :

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Using Quartus ii 13.0 reading project file written DS18B20 will read the results displayed on the LCD and stored in RAM.
Update : 2025-01-21 Size : 3.65mb Publisher :

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viterbi verilog implemetation based matlab
Update : 2025-01-21 Size : 1.04mb Publisher : kim jan

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FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, counters, latches, and display the data select
Update : 2025-01-21 Size : 6.35mb Publisher : 郑晓

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Write your own convolution code, simulation results can be achieved
Update : 2025-01-21 Size : 3.58mb Publisher : yanhui

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AD7606 state machine drive, verilog code, can be normal use.
Update : 2025-01-21 Size : 3kb Publisher : 小波

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Verilog language FPGA serial transceiver module, I can receive can send also to change the baud rate
Update : 2025-01-21 Size : 345kb Publisher : 张旭

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Verilog language to write a game in which can run on the FPGA.
Update : 2025-01-21 Size : 1.22mb Publisher : 张旭

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Simple serial port to receive, transmit program that can send and receive, you can test by
Update : 2025-01-21 Size : 319kb Publisher : chen

lattice ECP3 series high speed serdes test code
Update : 2025-01-21 Size : 5.17mb Publisher : 崔佰顺
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