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VHDL-FPGA-Verilog list
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The serial communication of FPGA program and Platform for XILINX SPANTAN-6, compressed package with specific documentation.
Update : 2025-01-25 Size : 366kb Publisher : 刘冰

CPLD and CY7C68013 communication program that uses synchronous input function test can be used, you need to download the firmware automatically synchronized into.
Update : 2025-01-25 Size : 163kb Publisher : 刘冰

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NIOS based engineering cyclone 2
Update : 2025-01-25 Size : 12.08mb Publisher : 翟磊

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Serial transmission control program!
Update : 2025-01-25 Size : 510kb Publisher : 邓智友

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Serial port to receive program source code, the actual verification of the final version after receiving operation!
Update : 2025-01-25 Size : 1.1mb Publisher : 邓智友

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Verilog based distress signal written in sos, apply quartus ii development environment!
Update : 2025-01-25 Size : 582kb Publisher : 邓智友

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Based on the SignalTap quartus ii test documentation, full test series after the file!
Update : 2025-01-25 Size : 1.78mb Publisher : 邓智友

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In the development environment for verilog pwm signal duty cycle regulated write debugging!
Update : 2025-01-25 Size : 514kb Publisher : 邓智友

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communication between FPGA and DAC max5309
Update : 2025-01-25 Size : 2kb Publisher : 王志映

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Privileged EP1C development board to achieve digital photo frame features plus gray, with verilog programming.
Update : 2025-01-25 Size : 9.96mb Publisher : 朱朴宁

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EDA small program design using VHDL seven people voting, four adder.
Update : 2025-01-25 Size : 1kb Publisher : 露露

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EDA curriculum design, as the seconds counter system clock 512Hz, stopwatch count as two BCD counting, counting and processing has reduced counting function
Update : 2025-01-25 Size : 59kb Publisher : 露露
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