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VHDL-FPGA-Verilog list
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low-power 16-bit CMOS D/A converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is
Update : 2025-01-25 Size : 624kb Publisher : john

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With DE2 board with SW0 to 1 indicates the desired letter, KEY1 running red lights display the corresponding Morse code, KEY0 reset
Update : 2025-01-25 Size : 1kb Publisher : 何亦嘉

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You can use this to display the image you want to display on the screen. Can also be used to make the animation (painting a rub a painting and then move again)
Update : 2025-01-25 Size : 12kb Publisher : 何亦嘉

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qsys with mmu mpu. Design in SOPC quartus 9.0
Update : 2025-01-25 Size : 13.92mb Publisher : jcc18

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as the same as its name
Update : 2025-01-25 Size : 1.83mb Publisher : 郑岩

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Using synthesizable Verilog coding a digital clock with alarm. It has the following features: 1) timing functions include: hours, minutes, seconds. 2) When the school functions: hours, minutes and seconds to the manual c
Update : 2025-01-25 Size : 2kb Publisher : shikai

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VHDL floating point division, source code, including simulation map
Update : 2025-01-25 Size : 121kb Publisher : 钓江雪

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These codes are uart code written by verilog
Update : 2025-01-25 Size : 3.22mb Publisher : bdse98

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Microblaze hardware
Update : 2025-01-25 Size : 18.05mb Publisher : fzm

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minimalistic mips core. you can load it to any fpga.
Update : 2025-01-25 Size : 487kb Publisher : aineko

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FPGA implementation details with VGA interface and display pictures
Update : 2025-01-25 Size : 584kb Publisher : 王三木

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FFT algorithm is described in detail and with FPGA implementations, including FFT algorithm introduced
Update : 2025-01-25 Size : 1.17mb Publisher : 王三木
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