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VHDL-FPGA-Verilog list
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Realized under the control of six LCD clock display correctly count
Update : 2025-01-29 Size : 557kb Publisher : wangxiao

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This is a simple 8-bit CPU verilog source code,which includes user s guide.
Update : 2025-01-29 Size : 2.46mb Publisher : Yan Tian

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本程序是在FPGA里面模拟RS232串口,并在已调试成功
Update : 2014-12-29 Size : 2.57kb Publisher : yuzhan3861@126.com

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Carry look a head adder Verilog
Update : 2025-01-29 Size : 184kb Publisher : bakka

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booth 4 bits programmed by verilog and simulated using ISE software and no implemented
Update : 2025-01-29 Size : 389kb Publisher : bakka

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control eight lights,change eight form
Update : 2025-01-29 Size : 1.19mb Publisher : wangxiao

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SPI Verilog implementation, good code.
Update : 2025-01-29 Size : 649kb Publisher : mxc

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CRC algorithm based on verilog.
Update : 2025-01-29 Size : 1kb Publisher : mxc

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The three section type of typical state machine method, Verilog implementation
Update : 2025-01-29 Size : 1kb Publisher : mxc

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The pipelined implementation, based on Verilog language.
Update : 2025-01-29 Size : 1kb Publisher : mxc

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Implementation mechanism of ROM model, based on Verilog language.
Update : 2025-01-29 Size : 1kb Publisher : mxc

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Using ALTERA FPGA implementation of CF, speaking, reading and writing operations
Update : 2025-01-29 Size : 5.47mb Publisher : 何俊
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