VHDL-FPGA-Verilog List Page 643

VHDL-FPGA-Verilog list

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double_closed_loop Downloaded：0: based on zynq_7000 fpga-MOTOR CONTROL
Update : 2025-01-30 Size : 193kb Publisher : 葛明明
RS-encoder Downloaded：0: RSC encoder in VHDL. Hope it helpful.
Update : 2025-01-30 Size : 4kb Publisher : thang
V2.tar Downloaded：2: SDIO slave, written in verilog, does not support SPI mode.
Update : 2025-01-30 Size : 9kb Publisher : corgano
APB_slave Downloaded：0: APB slave template for AMBA bus written in Verilog
Update : 2025-01-30 Size : 1kb Publisher : corgano
or1200.tar Downloaded：0: OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
Update : 2025-01-30 Size : 3.52mb Publisher : corgano
verilog-arbiter.tar Downloaded：0: Verilog arbitrator for Wishbone R3 compliant bus
Update : 2025-01-30 Size : 5kb Publisher : corgano
wb_sdram_ctrl.tar Downloaded：0: Generic Wishbone R3 compliant SDRAM controller written in Verilog
Update : 2025-01-30 Size : 10kb Publisher : corgano
bt656_to_yuv422 Downloaded：1: bt656 internel sync to extern sync singal， bt656 internel sync to extern sync singal
Update : 2025-01-30 Size : 1kb Publisher : zbunix
bt656_timing_analysis Downloaded：0: The video standard ITU-R.656 timing analysis
Update : 2025-01-30 Size : 81kb Publisher : zbunix
Basys2Lcd Downloaded：0: This the file of controling a LCD display of Basys2 board used to pass the exams of VHDL
Update : 2025-01-30 Size : 1kb Publisher : plaukuotis
pingpong Downloaded：0: Use Verilog HDL to achieve a table tennis game, and through the verification on the DE2 development board.
Update : 2025-01-30 Size : 1.72mb Publisher : 杨震
fpga-usb-verilog-test Downloaded：0: Red hurricane development board of the USB test source code, including documentation, FPGA verilog code, cy68013 firmware program, PC test program. Realization of USB loopback test, which can be taken as reference to the
Update : 2025-01-30 Size : 15.16mb Publisher : 贾程序

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