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VHDL-FPGA-Verilog list
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HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement
Update : 2025-01-31 Size : 180kb Publisher : zhouyu

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This program implements 1278 AD sampling chip and FPGA communication, written in accordance with the timing on the datasheet.
Update : 2025-01-31 Size : 1.06mb Publisher : 常跃跃

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Reform program will achieve two Manchester encoded signal to a validated using simulation software
Update : 2025-01-31 Size : 85kb Publisher : 常跃跃

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31 single-cycle instruction CPU
Update : 2025-01-31 Size : 63kb Publisher : Liu Ao

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Using ISE software development board wrote in basys2 counter mold 60
Update : 2025-01-31 Size : 1.8mb Publisher : liwenqi

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Four decimal frequency machines, automatic frequency measurement, latch, clear function
Update : 2025-01-31 Size : 1.13mb Publisher : 郭永峰

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Decoder function to achieve 38
Update : 2025-01-31 Size : 113kb Publisher : 董怡静

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vhdl code written fpga realize Butterfly music player
Update : 2025-01-31 Size : 685kb Publisher : 宋力

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Achieve a Coke vending machine soda, including the clock divider, automatic change, the ability to sell successfully, and other functions. Exercise is one of the basic movement of Information Engineering, Sun Yat-digital
Update : 2025-01-31 Size : 8.28mb Publisher : jintaoluo

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The implementation of adders. Experiment of SMIE.
Update : 2025-01-31 Size : 547kb Publisher : Wangchy

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Another implementation of adder in verilog
Update : 2025-01-31 Size : 556kb Publisher : Wangchy

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Use verilog to implemwnt a soda_machine
Update : 2025-01-31 Size : 1.87mb Publisher : Wangchy
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