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VHDL-FPGA-Verilog list
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tx buffer inband VHDL
Update : 2025-02-21 Size : 2kb Publisher : zhou tao

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VERILOG Practical cases, about 135, particularly useful for beginners
Update : 2025-02-21 Size : 25kb Publisher : yubo

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100MHZ clock signal through a divider to get 1HZ signal, and then input to the three counters, the output of the counter displayed on the corresponding LED lights on the FPGA. The program consists of four main parts: the
Update : 2025-02-21 Size : 1kb Publisher : asong

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-Simple CPU design of the VHDL code and VHDL design process cpu
Update : 2025-02-21 Size : 2.42mb Publisher : woshi

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High-precision DC source, DAC1220,20 bit resolution, bipolar output
Update : 2025-02-21 Size : 321kb Publisher : 慕容麒脩

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Verilog Code for Receiver USART
Update : 2025-02-21 Size : 1kb Publisher : Tushar

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Verilog Code for Transmitter USART
Update : 2025-02-21 Size : 1kb Publisher : Tushar

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This program uses the always statement to realize 3-8 decoder function, simulation waveform is right.
Update : 2025-02-21 Size : 119kb Publisher : Dr.Shang

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This program uses the assign statement to realize 3-8 decoder function, simulation waveform is right.
Update : 2025-02-21 Size : 127kb Publisher : Dr.Shang

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the 16 bits cordic codes in VHDL
Update : 2025-02-21 Size : 1kb Publisher : 郭凯丰

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The FPGA 2048 points FFT algorithm
Update : 2025-02-21 Size : 5.16mb Publisher : xie qiongfei

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asyn_fifo include detailed instruction,Synchronous FIFO for TPRAM
Update : 2025-02-21 Size : 380kb Publisher : 杨莉莉
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