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VHDL-FPGA-Verilog list
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Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64
Update : 2025-01-31 Size : 175kb Publisher : 静水沉沙

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Using OV7670 camera video data sampled by FPGA DE2 development board with a VGA display on the screen.
Update : 2025-01-31 Size : 924kb Publisher : jack chen

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Design and Simulation of 8-bit RISC microprocessors, reduced instruction set
Update : 2025-01-31 Size : 1.74mb Publisher : Bonnie

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this code is used for implementation of barrel shifter using verilog language
Update : 2025-01-31 Size : 2kb Publisher : appolo

implementation of 8bit adder with pararel computation. It s use S/P converter and P/S converter. The code is written in verilog language
Update : 2025-01-31 Size : 1kb Publisher : appolo

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implementation of cordic algorithm for many aplication like cos, sinus, polar to rectangular conversion and rectangular to polar conversion. It s written in verilog language and testbench is included
Update : 2025-01-31 Size : 3kb Publisher : appolo

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Digital synthesizer (DDS) based on FPGA, using VHDL language, to achieve sine wave, triangle wave, square wave, sawtooth waveform generation four. Tip: The last output module is a serial DA, may change depending on the d
Update : 2025-01-31 Size : 2.67mb Publisher : 康二栋

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Based on CORDIC achieve sinusoidal signal simulation by using built-in IP core CORDIC can achieve sinusoidal signal.
Update : 2025-01-31 Size : 5.66mb Publisher : 康二栋

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VGA display board and a stripe pattern. Through experiments panel button switch, enabling graphics switching VGA for beginners.
Update : 2025-01-31 Size : 633kb Publisher : 康二栋

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Music player, play a nice Butterfly Lovers , so that we learn of the player in the production of a good mood.
Update : 2025-01-31 Size : 282kb Publisher : 康二栋

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TFT scraper simple experiments, the TFT timing control, it is switched between red and blue. After a simple transformation can be used as a more powerful drive module.
Update : 2025-01-31 Size : 1.28mb Publisher : 康二栋

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Sine wave Generator using the direct digital synthesis Method
Update : 2025-01-31 Size : 153kb Publisher : rss.nitk
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