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VHDL-FPGA-Verilog list
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cube root
Update : 2025-02-01 Size : 3.1mb Publisher : Neddy

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SocKit FPGA with ARM core
Update : 2025-02-01 Size : 16.37mb Publisher : Neddy

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System C for FPGA
Update : 2025-02-01 Size : 516kb Publisher : Neddy

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Network on chip router code part1
Update : 2025-02-01 Size : 17kb Publisher : jack

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1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request
Update : 2025-02-01 Size : 106kb Publisher : YINJIE

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Learn to use the structure described methods (hierarchical design), design 4 binary counter 7-segment display decoder learn and master module instantiation statement applications.
Update : 2025-02-01 Size : 99kb Publisher : YINJIE

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With a state machine sequence detector design, understand the design and application of finite state machines.
Update : 2025-02-01 Size : 195kb Publisher : YINJIE

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Use QuartusⅡ completed 2-to-1 multiplexer input text editing and simulation testing and other steps, given the simulation waveform.
Update : 2025-02-01 Size : 282kb Publisher : YINJIE

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This file contains digital sampling filter cic verilog code, after testing is available, and the introduction, less consumption of hardware resources.
Update : 2025-02-01 Size : 1kb Publisher : 张俊

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The program for the entire ship navigation radar system timing control module contains the QPF project.
Update : 2025-02-01 Size : 3.85mb Publisher : 鲁文芳

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This procedure for the marine navigation radar antenna part of the Verilog program, including QPF works.
Update : 2025-02-01 Size : 8.81mb Publisher : 鲁文芳

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Based verilog generate multiple PWM waveform.
Update : 2025-02-01 Size : 1.63mb Publisher : 汪杰
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