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VHDL-FPGA-Verilog list
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contains a divider on the frequency that can be obtained at 13.5 MHz output if the input signal is applied to a 40 MHz
Update : 2025-02-01 Size : 998kb Publisher : Mo11

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The program to control development board counts up four digital tube, cleared 0000-9999, after overflow
Update : 2025-02-01 Size : 501kb Publisher : 郭功勋

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The program control development in turn led panel lights, to the effect of light water
Update : 2025-02-01 Size : 434kb Publisher : 郭功勋

verilog HDL language program, you can control led and digital synchronous beating
Update : 2025-02-01 Size : 395kb Publisher : 郭功勋

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Control crossroads traffic lights, with the fpga realize, verilog language, can achieve control of red, green and yellow in both directions left lamp.
Update : 2025-02-01 Size : 230kb Publisher : allen

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FPGA design based on sinusoidal signal generator with verilog language, adjust the frequency and period.
Update : 2025-02-01 Size : 590kb Publisher : allen

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FPGA-based frequency meter, using verilog language, the standard clock counted to obtain the frequency of the signal.
Update : 2025-02-01 Size : 222kb Publisher : allen

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FPGA-based design of digital voltmeter. ADC0809 with FPGA complete control, measure voltage, and digital tube display.
Update : 2025-02-01 Size : 144kb Publisher : allen

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FPGA-based local bus interface. Based fifo contains two programs and the general register.
Update : 2025-02-01 Size : 324kb Publisher : wang

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It is written in their own dds source, using a lookup table method, pro-test available.
Update : 2025-02-01 Size : 5.49mb Publisher : xiezhuneng

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A 18bit*18bit booth2 mutiplixer
Update : 2025-02-01 Size : 15kb Publisher : yefeng

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A pipeline sturcture GCD DAC, data width is 32bit.
Update : 2025-02-01 Size : 4kb Publisher : yefeng
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