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Packet : 91331990niosii_lab.rar filelist
NIOSII_lab\Altera\Designing with Quartus Labs(UP3).doc
NIOSII_lab\Altera\IP\Sram_UP3\class.ptf
NIOSII_lab\Altera\IP\Sram_UP3\mk_sram.pl
NIOSII_lab\Altera\IP\UP3_Board\class.ptf
NIOSII_lab\Altera\IP\UP3_Board\system\cmp_state.ini
NIOSII_lab\Altera\IP\UP3_Board\system\cpu_0.ocp
NIOSII_lab\Altera\IP\UP3_Board\system\cpu_0.v
NIOSII_lab\Altera\IP\UP3_Board\system\cpu_0_gen_log_0.txt
NIOSII_lab\Altera\IP\UP3_Board\system\cpu_0_test_bench.v
NIOSII_lab\Altera\IP\UP3_Board\system\data_RAM.hex
NIOSII_lab\Altera\IP\UP3_Board\system\data_RAM.v
NIOSII_lab\Altera\IP\UP3_Board\system\firmware_ROM.hex
NIOSII_lab\Altera\IP\UP3_Board\system\firmware_ROM.v
NIOSII_lab\Altera\IP\UP3_Board\system\jtag_uart_0.v
NIOSII_lab\Altera\IP\UP3_Board\system\payload_buffer.hex
NIOSII_lab\Altera\IP\UP3_Board\system\payload_buffer.v
NIOSII_lab\Altera\IP\UP3_Board\system\pin_assign.tcl
NIOSII_lab\Altera\IP\UP3_Board\system\pin_assign.tcl.bak
NIOSII_lab\Altera\IP\UP3_Board\system\rf_ram.mif
NIOSII_lab\Altera\IP\UP3_Board\system\sopc_builder_debug_log.txt
NIOSII_lab\Altera\IP\UP3_Board\system\sysid.v
NIOSII_lab\Altera\IP\UP3_Board\system\undo_redo.txt
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.asm.rpt
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.bsf
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.done
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.fit.eqn
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.fit.rpt
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.fit.summary
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.flow.rpt
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.map.eqn
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.map.rpt
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.map.summary
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.pin
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.pof
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.ptf
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.ptf.4.01
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.ptf.bak
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.qpf
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.qsf
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.qws
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.sof
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.tan.rpt
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.tan.summary
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board.v
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_assignment_defaults.qdf
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_generation_script
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_log.txt
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_setup_quartus_native_synthesis.tcl
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_sim\contents_file_warning.txt
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_sim\jtag_uart_0_input_mutex.dat
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_sim\jtag_uart_0_input_stream.dat
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_sim\jtag_uart_0_output_stream.dat
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_time_limited.sof
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_top.bdf
NIOSII_lab\Altera\NiosII_lab\avalon_pwm.v
NIOSII_lab\Altera\NiosII_lab\cmp_state.ini
NIOSII_lab\Altera\NiosII_lab\crc.bdf
NIOSII_lab\Altera\NiosII_lab\crc_mux.bdf
NIOSII_lab\Altera\NiosII_lab\crc_peripheral.v
NIOSII_lab\Altera\NiosII_lab\crc_peripheral.vhd
NIOSII_lab\Altera\NiosII_lab\custominstruction_cpu.vhd
NIOSII_lab\Altera\NiosII_lab\db\NiosII_lab.db_info
NIOSII_lab\Altera\NiosII_lab\db\NiosII_lab.map.qmsg
NIOSII_lab\Altera\NiosII_lab\db\NiosII_lab.project.hdb
NIOSII_lab\Altera\NiosII_lab\db\NiosII_lab.sld_design_entry.sci
NIOSII_lab\Altera\NiosII_lab\endian_convert.bdf
NIOSII_lab\Altera\NiosII_lab\for_UP3.bsf
NIOSII_lab\Altera\NiosII_lab\for_UP3.v
NIOSII_lab\Altera\NiosII_lab\NiosII_lab.bdf
NIOSII_lab\Altera\NiosII_lab\NiosII_lab.done
NIOSII_lab\Altera\NiosII_lab\NiosII_lab.qpf
NIOSII_lab\Altera\NiosII_lab\NiosII_lab.qsf
NIOSII_lab\Altera\NiosII_lab\NiosII_lab.qws
NIOSII_lab\Altera\NiosII_lab\NiosII_lab_assignment_defaults.qdf
NIOSII_lab\Altera\NiosII_lab\reg16.bdf
NIOSII_lab\Altera\NiosII_lab\Setup_Cyclone_1C6.tcl
NIOSII_lab\Altera\NiosII_lab\software\altera_avalon_pwm.h
NIOSII_lab\Altera\NiosII_lab\software\crc.c
NIOSII_lab\Altera\NiosII_lab\software\crcci.c
NIOSII_lab\Altera\NiosII_lab\software\crcdma.c
NIOSII_lab\Altera\NiosII_lab\software\pwm.c
NIOSII_lab\Altera\NiosII_lab\software\simple.c
NIOSII_lab\Altera\NiosII_lab\xor_shift_crc16_ccitt.bdf
NIOSII_lab\Altera\IP\UP3_Board\system\db
NIOSII_lab\Altera\IP\UP3_Board\system\UP3_Board_sim
NIOSII_lab\Altera\IP\UP3_Board\system
NIOSII_lab\Altera\IP\Sram_UP3
NIOSII_lab\Altera\IP\UP3_Board
NIOSII_lab\Altera\NiosII_lab\db
NIOSII_lab\Altera\NiosII_lab\software
NIOSII_lab\Altera\IP
NIOSII_lab\Altera\NiosII_lab
NIOSII_lab\Altera
NIOSII_lab

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