FPGA and SOPC based on the use of VHDL language EDA sinusoidal signal generator

Packet : 57578876expt71_singt.rar filelist
EXPT71_SINGT
EXPT71_SINGT\DATA_ROM.VHD
EXPT71_SINGT\GG.MIF
EXPT71_SINGT\SIM.CFG
EXPT71_SINGT\SINGT.CDF
EXPT71_SINGT\SINGT.PIN
EXPT71_SINGT\SINGT.QPF
EXPT71_SINGT\SINGT.QSF
EXPT71_SINGT\SINGT.QWS
EXPT71_SINGT\SINGT.SOF
EXPT71_SINGT\SINGT.VHD
EXPT71_SINGT\SINGT.VWF
EXPT71_SINGT\SINGT.asm.rpt
EXPT71_SINGT\SINGT.done
EXPT71_SINGT\SINGT.flow.rpt
EXPT71_SINGT\SINGT.map.rpt
EXPT71_SINGT\SINGT.map.summary
EXPT71_SINGT\SINGT.tan.summary
EXPT71_SINGT\STP1.STP
EXPT71_SINGT\STP2.STP
EXPT71_SINGT\cmp_state.ini
EXPT71_SINGT\dataHEX
EXPT71_SINGT\dataHEX\SDATA.ASM
EXPT71_SINGT\dataHEX\SDATA.BIN
EXPT71_SINGT\dataHEX\SDATA.HEX
EXPT71_SINGT\dataHEX\SDATA.LST

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