FPGA and SOPC based on the use of VHDL language EDA s DDS Signal Generator

Packet : 117143199expt12_9_dds.rar filelist
EXPT12_9_DDS
EXPT12_9_DDS\ADDER10B.VHD
EXPT12_9_DDS\ADDER32B.VHD
EXPT12_9_DDS\DDS.CDF
EXPT12_9_DDS\DDS.PIN
EXPT12_9_DDS\DDS.QPF
EXPT12_9_DDS\DDS.QSF
EXPT12_9_DDS\DDS.QWS
EXPT12_9_DDS\DDS.SOF
EXPT12_9_DDS\DDS.VHD
EXPT12_9_DDS\LUT10X10.HEX
EXPT12_9_DDS\LUT10X10.MIF
EXPT12_9_DDS\REG10B.VHD
EXPT12_9_DDS\REG32B.VHD
EXPT12_9_DDS\SIN_ROM.BSF
EXPT12_9_DDS\SIN_ROM.VHD
EXPT12_9_DDS\STP1.STP
EXPT12_9_DDS\cmp_state.ini
EXPT12_9_DDS\dds.asm.rpt
EXPT12_9_DDS\dds.done
EXPT12_9_DDS\dds.fit.summary
EXPT12_9_DDS\dds.flow.rpt
EXPT12_9_DDS\dds.map.summary
EXPT12_9_DDS\dds.tan.summary
EXPT12_9_DDS\DATA
EXPT12_9_DDS\DATA\LUT10X10.HEX
EXPT12_9_DDS\DATA\LUT10X10.MIF
EXPT12_9_DDS\README
EXPT12_9_DDS\README\GW48使用readme.txt

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