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VHDL-FPGA-Verilog
Title:
基于MIPS指令集的五级流水线
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Category:
VHDL编程
Tags:
[ASM]
[源码]
File Size:
138.25kb
Update:
2013-07-02
Downloads:
0 Times
Uploaded by:
cjc87267137
Description:
运用verilog语言实现的MIPS指令集,包括加、减、比较、与、异或等指令。运用五级流水线,设置IF,ID,EX,MEM、WB五个栈间计算模块。运用了forwarding和stop技术。可以使用modelsim验证。
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