ALTERA FPGA/CPLD High chapter high-speed DDR memory data interface design example

Packet : 25811242ddrinterface.rar filelist
Core\EPLL.bsf
Core\EPLL.v
Core\EPLL_bb.v
Core\EPLL_inst.v
Core\MY_DQ.bsf
Core\MY_DQ.v
Core\MY_DQS.bsf
Core\MY_DQS.v
Core\MY_DQS_bb.v
Core\MY_DQS_inst.v
Core\MY_DQ_bb.v
Core\MY_DQ_inst.v
Project\DataPath.bdf
Project\DataPath.qpf
Project\DataPath.qsf
Core
Project

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