AD7682 FPGA program 4 channels using official procedures using internal benchmarks

DataCapture
DataCapture\data_capture.bat
DataCapture\data_capture.tcl
EvalBoardFPGA
EvalBoardFPGA\AD7682.v
EvalBoardFPGA\CED1Z_interface.v
EvalBoardFPGA\Docs
EvalBoardFPGA\Docs\AD7682.pdf
EvalBoardFPGA\EPCS4Active.cof
EvalBoardFPGA\EvalBoardAD7682.cdf
EvalBoardFPGA\EvalBoardAD7682.done
EvalBoardFPGA\EvalBoardAD7682.fit.smsg
EvalBoardFPGA\EvalBoardAD7682.jdi
EvalBoardFPGA\EvalBoardAD7682.map
EvalBoardFPGA\EvalBoardAD7682.map.smsg
EvalBoardFPGA\EvalBoardAD7682.pin
EvalBoardFPGA\EvalBoardAD7682.pof
EvalBoardFPGA\EvalBoardAD7682.qpf
EvalBoardFPGA\EvalBoardAD7682.qsf
EvalBoardFPGA\EvalBoardAD7682.qws
EvalBoardFPGA\EvalBoardAD7682.sdc
EvalBoardFPGA\EvalBoardAD7682.sof
EvalBoardFPGA\EvalBoard_top.v
EvalBoardFPGA\EvalBoard_top.v.bak
EvalBoardFPGA\pll.bsf
EvalBoardFPGA\pll.cmp
EvalBoardFPGA\pll.inc
EvalBoardFPGA\pll.ppf
EvalBoardFPGA\pll.qip
EvalBoardFPGA\pll.v
EvalBoardFPGA\simulation
EvalBoardFPGA\simulation\TestBench
EvalBoardFPGA\simulation\TestBench\ad7682_model.v
EvalBoardFPGA\simulation\TestBench\ad7682_model_testbench.v
EvalBoardFPGA\simulation\TestBench\ad7682_tst.v
EvalBoardFPGA\simulation\TestBench\driver_state_radix
EvalBoardFPGA\simulation\TestBench\EvalBoard_top_tst.v
EvalBoardFPGA\simulation\TestBench\model_state_radix
FPGA
FPGA\ADIEvalBoard.elf
FPGA\ced1z.jdi
FPGA\ced1z.sof
FPGA\ip
FPGA\ip\AD7682
FPGA\ip\AD7682\Docs
FPGA\ip\AD7682\Docs\AD7682.pdf
FPGA\ip\AD7682\hdl
FPGA\ip\AD7682\hdl\src
FPGA\ip\AD7682\hdl\src\ad7682top_hw.tcl
FPGA\ip\AD7682\hdl\src\ad7682top_hw.tcl~
FPGA\ip\AD7682\hdl\src\AD7682_Avalon_core.v
FPGA\ip\AD7682\hdl\src\AD7682_sw.tcl
FPGA\ip\AD7682\hdl\src\Eval_Board_interface.v
FPGA\ip\AD7682\hdl\src\HAL
FPGA\ip\AD7682\hdl\src\HAL\inc
FPGA\ip\AD7682\hdl\src\HAL\inc\ad7682.h
FPGA\ip\AD7682\hdl\src\HAL\src
FPGA\ip\AD7682\hdl\src\HAL\src\ad7682.c
FPGA\ip\AD7682\hdl\src\HAL\src\component.mk
FPGA\ip\AD7682\hdl\src\inc
FPGA\ip\AD7682\hdl\src\inc\ad7682_regs.h
FPGA\ip\AD7682\hdl\src\write_master.v
FPGA\ip\AD7682\hdl\tb
FPGA\ip\AD7682\hdl\tb\AD7682.vt
FPGA\program_fpga.bat
FPGA\uC.sopcinfo
Hdl
Hdl\doc
Hdl\doc\AD7682.pdf
Hdl\src
Hdl\src\AD7682_Avalon_core.v
Hdl\src\Eval_Board_interface.v
Hdl\src\write_master.v
Hdl\tb
Hdl\tb\AD7682.vt
NiosCpu
NiosCpu\ced1z.cdf
NiosCpu\ced1z.done
NiosCpu\ced1z.jdi
NiosCpu\ced1z.map.smsg
NiosCpu\ced1z.pin
NiosCpu\ced1z.pof
NiosCpu\ced1z.qpf
NiosCpu\ced1z.qsf
NiosCpu\ced1z.qws
NiosCpu\ced1z.sdc
NiosCpu\ced1z.sof
NiosCpu\ced1z.v
NiosCpu\ced1z.v.bak
NiosCpu\ced1z_assignment_defaults.qdf
NiosCpu\cpu.v
NiosCpu\cpu_jtag_debug_module_sysclk.v
NiosCpu\cpu_jtag_debug_module_tck.v
NiosCpu\cpu_jtag_debug_module_wrapper.v
NiosCpu\cpu_ociram_default_contents.mif
NiosCpu\cpu_oci_test_bench.v
NiosCpu\cpu_rf_ram_a.mif
NiosCpu\cpu_rf_ram_b.mif
NiosCpu\cpu_test_bench.v
NiosCpu\debug.qip

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