PLL, pll. It's an important resource in FPGA. Because a complex FPGA system often requires multiple clock signals with different frequencies and phases. Therefore, the number of PLL in a FPGA chip is an important indicator of the ability of FPGA chip. In the design of FPGA, the high speed design of clock system FPGA is extremely important. A low jitter and low delay system clock will increase the success rate of FPGA design. This routine calls the PLL core provided by Xilinx to generate clocks of different frequencies, and outputs one of the clocks to the external IO of the FPGA, that is, the SMA interface of the development board.

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