A sequence signal generator and a sequence signal detector are designed using Verilog language, both of which are implemented in a state machine mode. The sequence signal generator outputs an 8-bit wide sequence signal "10110110", which is displayed through the digital tube; the output of the sequence signal generator is connected to the sequence signal detector, the detector detects the current input signal, and if the target sequence signal appears, it passes through the bee. The horn emits a sound indicating that a valid target signal has been detected.

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fff\incremental_db\compiled_partitions\abc.root_partition.map.hdb	13292	2017-12-18
fff\incremental_db\compiled_partitions\abc.root_partition.map.kpt	2205	2017-12-19
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fff\output_files\abc.flow.rpt	7000	2017-12-19
fff\output_files\abc.jdi	222	2017-12-19
fff\output_files\abc.map.rpt	26775	2017-12-19

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