A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the phase.

Filename	Size	Update
dpll源程序.txt	4342	2018-02-27

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．