Software Radio USRP v4.2 version of the hardware schematic diagram, including clock, debug board, fpga, interface, power and other parts, there are pdf, sch, ps, such as a variety of formats.

Packet : 57578855usrp_rev_4_2.rar filelist
USRP_REV_4_2\ChangeLog
USRP_REV_4_2\clock.pdf
USRP_REV_4_2\clock.ps
USRP_REV_4_2\clock.sch
USRP_REV_4_2\dboard.pdf
USRP_REV_4_2\dboard.ps
USRP_REV_4_2\dboard.sch
USRP_REV_4_2\fpga.pdf
USRP_REV_4_2\fpga.ps
USRP_REV_4_2\fpga.sch
USRP_REV_4_2\gafrc
USRP_REV_4_2\interface.pdf
USRP_REV_4_2\interface.ps
USRP_REV_4_2\interface.sch
USRP_REV_4_2\netlist_cmd
USRP_REV_4_2\power.pdf
USRP_REV_4_2\power.ps
USRP_REV_4_2\power.sch
USRP_REV_4_2\usrp-bom.xls
USRP_REV_4_2\usrp_mboard.bom
USRP_REV_4_2\usrp_mboard.net
USRP_REV_4_2\xy\bottom-assembly.pdf
USRP_REV_4_2\xy\bottom-assembly.pho
USRP_REV_4_2\xy\bottom.xy
USRP_REV_4_2\xy\camplus.rep
USRP_REV_4_2\xy\top-assembly.pdf
USRP_REV_4_2\xy\top-assembly.pho
USRP_REV_4_2\xy\top.xy
USRP_REV_4_2\xy\_svn\all-wcprops
USRP_REV_4_2\xy\_svn\entries
USRP_REV_4_2\xy\_svn\format
USRP_REV_4_2\xy\_svn\prop-base\bottom-assembly.pdf.svn-base
USRP_REV_4_2\xy\_svn\prop-base\top-assembly.pdf.svn-base
USRP_REV_4_2\xy\_svn\text-base\bottom-assembly.pdf.svn-base
USRP_REV_4_2\xy\_svn\text-base\bottom-assembly.pho.svn-base
USRP_REV_4_2\xy\_svn\text-base\bottom.xy.svn-base
USRP_REV_4_2\xy\_svn\text-base\camplus.rep.svn-base
USRP_REV_4_2\xy\_svn\text-base\top-assembly.pdf.svn-base
USRP_REV_4_2\xy\_svn\text-base\top-assembly.pho.svn-base
USRP_REV_4_2\xy\_svn\text-base\top.xy.svn-base
USRP_REV_4_2\_svn\all-wcprops
USRP_REV_4_2\_svn\dir-prop-base
USRP_REV_4_2\_svn\entries
USRP_REV_4_2\_svn\format
USRP_REV_4_2\_svn\prop-base\clock.pdf.svn-base
USRP_REV_4_2\_svn\prop-base\interface.pdf.svn-base
USRP_REV_4_2\_svn\prop-base\netlist_cmd.svn-base
USRP_REV_4_2\_svn\prop-base\power.pdf.svn-base
USRP_REV_4_2\_svn\prop-base\usrp-bom.xls.svn-base
USRP_REV_4_2\_svn\text-base\ChangeLog.svn-base
USRP_REV_4_2\_svn\text-base\clock.pdf.svn-base
USRP_REV_4_2\_svn\text-base\clock.ps.svn-base
USRP_REV_4_2\_svn\text-base\clock.sch.svn-base
USRP_REV_4_2\_svn\text-base\dboard.pdf.svn-base
USRP_REV_4_2\_svn\text-base\dboard.ps.svn-base
USRP_REV_4_2\_svn\text-base\dboard.sch.svn-base
USRP_REV_4_2\_svn\text-base\fpga.pdf.svn-base
USRP_REV_4_2\_svn\text-base\fpga.ps.svn-base
USRP_REV_4_2\_svn\text-base\fpga.sch.svn-base
USRP_REV_4_2\_svn\text-base\gafrc.svn-base
USRP_REV_4_2\_svn\text-base\interface.pdf.svn-base
USRP_REV_4_2\_svn\text-base\interface.ps.svn-base
USRP_REV_4_2\_svn\text-base\interface.sch.svn-base
USRP_REV_4_2\_svn\text-base\netlist_cmd.svn-base
USRP_REV_4_2\_svn\text-base\power.pdf.svn-base
USRP_REV_4_2\_svn\text-base\power.ps.svn-base
USRP_REV_4_2\_svn\text-base\power.sch.svn-base
USRP_REV_4_2\_svn\text-base\usrp-bom.xls.svn-base
USRP_REV_4_2\_svn\text-base\usrp_mboard.bom.svn-base
USRP_REV_4_2\_svn\text-base\usrp_mboard.net.svn-base
USRP_REV_4_2\xy\_svn\tmp\prop-base
USRP_REV_4_2\xy\_svn\tmp\props
USRP_REV_4_2\xy\_svn\tmp\text-base
USRP_REV_4_2\xy\_svn\prop-base
USRP_REV_4_2\xy\_svn\props
USRP_REV_4_2\xy\_svn\text-base
USRP_REV_4_2\xy\_svn\tmp
USRP_REV_4_2\_svn\tmp\prop-base
USRP_REV_4_2\_svn\tmp\props
USRP_REV_4_2\_svn\tmp\text-base
USRP_REV_4_2\xy\_svn
USRP_REV_4_2\_svn\prop-base
USRP_REV_4_2\_svn\props
USRP_REV_4_2\_svn\text-base
USRP_REV_4_2\_svn\tmp
USRP_REV_4_2\xy
USRP_REV_4_2\_svn
USRP_REV_4_2

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