the development process is targeted mainly LCD design of the Multi-rate Initialization

Packet : 17869355niosii_cyclone_1c20.rar filelist
niosII_cyclone_1c20\quartus_project\11.qpf
niosII_cyclone_1c20\quartus_project\11.qsf
niosII_cyclone_1c20\quartus_project\db\11.db_info
niosII_cyclone_1c20\quartus_project\db\11.map.qmsg
niosII_cyclone_1c20\quartus_project\db\11.hif
niosII_cyclone_1c20\quartus_project\db\11.sld_design_entry_dsc.sci
niosII_cyclone_1c20\quartus_project\db\11.map.hdb
niosII_cyclone_1c20\quartus_project\db\11.cmp.rdb
niosII_cyclone_1c20\quartus_project\db\11_cmp.qrpt
niosII_cyclone_1c20\quartus_project\db\11.sld_design_entry.sci
niosII_cyclone_1c20\quartus_project\db\11.eco.cdb
niosII_cyclone_1c20\quartus_project\db
niosII_cyclone_1c20\quartus_project\sopc_builder_debug_log.txt
niosII_cyclone_1c20\quartus_project\system.ptf.4.01
niosII_cyclone_1c20\quartus_project\component_builder_logfile.txt
niosII_cyclone_1c20\quartus_project\first_nios2_system.ptf
niosII_cyclone_1c20\quartus_project\first_nios2_system.v
niosII_cyclone_1c20\quartus_project\first_nios2_system_log.txt
niosII_cyclone_1c20\quartus_project\11.qws
niosII_cyclone_1c20\quartus_project\cmp_state.ini
niosII_cyclone_1c20\quartus_project\first_nios2_system_sim\atail-f.pl
niosII_cyclone_1c20\quartus_project\first_nios2_system_sim\jtag_uart_input_stream.dat
niosII_cyclone_1c20\quartus_project\first_nios2_system_sim\jtag_uart_input_mutex.dat
niosII_cyclone_1c20\quartus_project\first_nios2_system_sim\jtag_uart_output_stream.dat
niosII_cyclone_1c20\quartus_project\first_nios2_system_sim
niosII_cyclone_1c20\quartus_project\ic_tag_ram.mif
niosII_cyclone_1c20\quartus_project\rf_ram_a.mif
niosII_cyclone_1c20\quartus_project\rf_ram_b.mif
niosII_cyclone_1c20\quartus_project\cpu_ociram_default_contents.mif
niosII_cyclone_1c20\quartus_project\cpu_test_bench.v
niosII_cyclone_1c20\quartus_project\cpu_jtag_debug_module.v
niosII_cyclone_1c20\quartus_project\cpu_jtag_debug_module_wrapper.v
niosII_cyclone_1c20\quartus_project\cpu.v
niosII_cyclone_1c20\quartus_project\cpu.ocp
niosII_cyclone_1c20\quartus_project\jtag_uart.v
niosII_cyclone_1c20\quartus_project\system_timer.v
niosII_cyclone_1c20\quartus_project\button_pio.v
niosII_cyclone_1c20\quartus_project\reconfig_request_pio.v
niosII_cyclone_1c20\quartus_project\lcd_pio.v
niosII_cyclone_1c20\quartus_project\led_pio.v
niosII_cyclone_1c20\quartus_project\seven_seg_pio.v
niosII_cyclone_1c20\quartus_project\first_nios2_system.bsf
niosII_cyclone_1c20\quartus_project\first_nios2_system_generation_script
niosII_cyclone_1c20\quartus_project\first_nios2_system_setup_quartus_native_synthesis.tcl
niosII_cyclone_1c20\quartus_project\11.map.rpt
niosII_cyclone_1c20\quartus_project\11.flow.rpt
niosII_cyclone_1c20\quartus_project\11.map.summary
niosII_cyclone_1c20\quartus_project
niosII_cyclone_1c20

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