Description: Logic Analyzer PC sent to the MCU orders were seven byte : the first byte of the trigger signal, every bit signal corresponding way, a trigger for the margin, 0 for low-level trigger; the second byte is effective trigger signal, every bit signal corresponding way, as a neglected, 0 for the effective; Third, the four bytes of sampling time counterparts are as follows : 2us = 0x0402, 5us = 0x0a02, 10us = 0x1402. 10us = 0x2802, 0x6402 = 50us, 100us = 0xc802. 200us = 0x3203, 500us = 0x7d03, 1ms = 0xfa03. PF = 0x7d04, 4ms = 0xfa04, 0x7d05 = 8ms, 0xfa05 = 16ms; Fifth, six byte is the same as that for pre-trigger : 8 = 0%, 7 = 12.5%. 6 = 25%, 5 = 37.5%, 4 = 50%, 3 = 62.5%, 2 = 75%, 1 = 87.5% for the seventh byte mode, the ordinary mode = 0; 1 = external clock, rose extension; 2 = external clock.
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