divider This code used to realize the base 2 SRT d

Title: divider

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
2.27kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
zhuql07

Description: This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.

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