Description: Realize the use of hardware, through the FPGA to verify the efficiency of higher adder,
- [CAN] - 80C196 MCU and transceiver CAN initializ
- [4_COMP] - The use of hardware implementation, the
- [FULLADD] - Full adder using Verilog
- [VHDL] - The vhdl source codes of ram,fifo.
- [FIR] - FIR filter VHDL source code and test fil
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