Description: Verilog I2C Bus realize, including the main module and several sub-modules have been simulation
- [ADPLL] - verilog ADPLL file with testbench.v
- [i2c_slave_model_verilog] - general website have i2c master module o
- [1_061026140305] - FPGA-based I2C bus simulation, using ver
- [VBtoEXCEL] - VB and EXCEL Introduction to seamlessly
- [I2C] - I2C Bus Principle and application exampl
- [i2c_Sample] - Verilog CPLD achieved in i2c master-slav
- [verilog] - Several languages to use Verilog HDL sou
- [i2c] - I2C is an engineering application that i
- [I2C_verilog] - Verilog design using a simple and practi
- [I2C] - Verilog I2C bus procedures, very useful,
File list (Check if you may need any files):