divider Based on the srt-2 algorithm, the use of V

Title: divider

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
2.86kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
liupx0606

Description: Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)

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