Description: Quartus 11 5.1 years in VHDL prepared using sine wave generator, through simulation through
- [Cadence_manual_1.2] - Cadence_manual_1.2.pdf
- [cn700_vc3484645] - bankers c algorithm used to prepare the
- [DDS234] - In this paper, using the VHDL-wave sine
- [msp430F149AD_DA_LCD] - sp430F149 the AD_DA_LCD data acquisition
- [mfsk] - vhdl mfsk M-ary digital frequency modula
- [VHDL] - This code can generate sine wave, triang
- [divider] - Based on the srt-2 algorithm, the use of
- [sin] - Quartus II 5.0 on the preparation of the
- [0522] - Their own design this year
- [dds] - FPGA realization of the use of DDS, sine
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