Description: This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder
- [BASED_FLEX10k20_cymometer] - Based on the frequency meter FLEX10K des
- [transt] - I have written as a decimal 16, hexadeci
- [g] - Has five students, each student has thre
- [add_16_bcd] - This procedure using VHDL language, comp
- [eecadd_8] - This procedure using VHDL language, the
- [d02] - This procedure for pulse width measureme
- [clock] - err
File list (Check if you may need any files):