Description: Contains RS (10,8) of the Verilog source code, the Verilog source code adder, convolution of the Verilog source code
- [ConvolutionalCodes,CRC] - convolution of C source code, including
- [juanjimabiancheng] - Matlab convolutional code compiler, the
- [fftipcore] - that the procedure was prepared by the v
- [RSverilog] - RS-coded Verilog source code, used to sh
- [coverlater] - This procedure is in circumstances Quart
- [rs-5-3] - Learning to use the FPGA to do a few sim
- [RSencoder] - Rs encoder code on the relevant procedur
- [RS(31-19-6)] - reed-solomon decoder. A total of seven p
- [rs_encode] - This is the verilog prepared using RS (2
- [viter2] - verilog to achieve the decoding convolut
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