Description: A serial communication program written with VHDL, including several different program examples, can be rewritten with verilog.
- [ uart from opencores] - VHDL implement serial port, it can commu
- [JG12864M] - jg12864mLCD display information source a
- [CleanFragments] - remove images of a small area (the noise
- [UART_source] - VHDL source files prepared by the UART,
- [spi] - SPI realize the functional VHDL source c
- [usb_xilinx_vhdl] - usb-source _xilinx_vhdl This is a Xilinx
- [uartsourcecode] - the FPGA UART modules, based on VHDL, ve
- [UART] - UART serial procedures, verilog statemen
- [uart] - FPGA-based UART controller, an optional
- [15Altera_IP] - Which contains 15 nuclear altera the IP
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