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Title:
examples
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
8.98kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
wang560114
Description:
Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
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