Description: Will be sinusoidal segmentation, digital processing, that is, dds technology, ready to do for the Verilog
- [EX_Text02] - This is a text output procedures, in a d
- [moon_ECI] - With the change of time, given the moon'
- [Sintab_Altera] - In the use of Verilog in the FPGA platfo
- [verilog_usbblaster] - Verilog prepared using USB download cabl
- [AD9851] - Using VHDL language DDS sine function ge
- [sine] - Verilog language prepared by the sine wa
- [Altera_training] - Altare company for training of new exerc
- [cic] - Verilog code written by CIC filter proce
- [1] - A typical course system, very useful, al
- [DDSverilogsource] - DDS of the Verilog source code, please s
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