Description: sin generator can produce sin in VHDL of the numerical waveform, and then make the conversion output to dac
- [usingVHDLtoimplementUART] - use of VHDL development of a UART of sou
- [dualportRAM] - dual-port RAM VHDL. Totally CPLD chip te
- [UART_source] - VHDL source files prepared by the UART,
- [sjb] - FPGA or CPLD with DAC (DAC0832), the sou
- [sn] - Xilinx ISE9.2 annex for the installation
- [128 × 16ram] - VHDL program designed RAM memory, dual p
- [uart] - UART code written in VHDL, experience ca
- [sin_any_w] - Prepared using VHDL procedures, arbitrar
- [dds] - CYCLONE II based on the procedure, DDS F
- [dpram2] - I write vhdl dual ram, true dual-port co
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