Description: In Quartus using D flip-flop to join the delay, each D flip-flop raised a half-cycle delay, a little change can be a different delay.
- [primetime] - This is the VHDL language delay the test
- [dff_UDP] - verilog achieve, UDP asynchronous reset
- [Eclipse] - Eclipse- Integrated Development Tool (th
- [JSP] - Essentials of a jsp, the jsp detailed ex
- [delay_line] - Delay-line module Verilog code, delay-li
- [dtrigger] - Common triggers- D flip-flop of VERILOG
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