Description: chdl 64 bit counter, using sine wave generated mif format. Sine wave can be simulated in FPGA
- [DDSFPGA_cylone] - dds design, spent a week doing, verilog
- [DDS_VHDL] - Written by a foreigner with CPLD realize
- [AM29LV160-320Flash] - AM29LV160 and AM29LV320 read, write and
- [frequency-phase_test_vhdl] - Phase tests, the frequency of testing, f
- [sine] - Verilog programming, the use of FPGA rea
- [javamails] - java development of e-mail system, there
- [clearlog] - Hackers learning books, to remove your r
- [dds] - CYCLONE II based on the procedure, DDS F
- [sin] - The sine wave generator based on FPGA de
- [sine-generator] - sine generator in quartus
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