Description: UART serial interface of the VHDL language with the simple realization, in the hope that everyone has to help
- [FPGAUART] - an FPGA-based serial procedures have pro
- [cy7c68013fpga] - BulkIn is the FPGA to the CY7C68013 is B
- [ethernet_tri_mode_rtl.tar] - Verilog realize asynchronous UART code,
- [RS232] - quatus II environment realize RS232 VHDL
- [SourceCode07_ExRam] - 2812 external data storage procedures to
- [example] - Several basic VHDL examples, including V
- [UART.ZIP] - serial port realized by vhdl.It has been
- [uart] - UART prepared Verilog source code. Succe
- [uart_module] - implement a smart UART interface
File list (Check if you may need any files):